1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to computer automated methods for checking integrated circuit layout masks.
2. Description of the Related Art
As the size of semiconductor device features continues to shrink and the demand for increased circuit density has correspondingly increased, semiconductor device designers have been turning to automated design tools, layout tools and checking tools. Because semiconductor devices are typically made by sequentially fabricating different device levels, a key task in designing a quality semiconductor device is to ensure that conductive vias used to interconnect a feature designed on a level below or a level above match up. Accordingly, because semiconductor devices have a very large number features, designers typically employ automated design rule checkers (DRCs) to verify that certain levels match up correctly. In general, before a layout design of a particular level is transferred onto a photolithography reticle, the design is in the form of a digital computer file, where each of the features have a plurality of associated X and Y coordinates that define their location on a mask.
To verify that successive levels match up, the DRC may perform logical comparisons between the coordinate mask layout files of each level to check whether a design rule has been violated. Exemplary design rules checking may include determinations of whether certain minimum inter-feature spacings have been violated, whether successive levels are overlapping, etc. Although DRCs are well suited to perform rapid checks over very large and complex layouts, current DRCs that check overlaps between a contact via level and an interconnect metal level require complete overlaps to avoid flagging an error. As such, designers typically design the interconnect metal line to be wider where a contact via will ultimately overlap. However, when interconnect metal lines are designed to be wider where contact vias overlap, the integrated circuit will necessarily be less dense, which thereby increases the size of a semiconductor chip.
With this in mind, FIG. 1A shows an upper level where metallization lines 12a and 12b are laid out, and a lower level where contact vias 14a and 14b are laid out. As shown, the metallization lines 12a and 12b have a Pitch.sub.1, and each line has a width Lw. In this manner, the two lines 12a and 12b have a minimum spacing (i.e., space (min)) that must be satisfied when the DRC examines the level on which the metallization line features are designed. When these features are still in the form of computer files having associated X and Y coordinates, the contact vias 14a and 14b that are designed on the lower level will match up (and overlap exactly) with the metallization lines 12a and 12b that lie in the upper level. Unfortunately, when these computer file designs are transferred to a photolithography reticle, and are then transferred as physical features on a semiconductor wafer, misalignments between the levels will unfortunately occur.
FIG. 1B illustrates the possible misalignments that may occur between the metallizationinilfs 12a' and 12b' and the contact vias 14a' and 14b' when transferred to a wafer. As is well known in the art, when feature patterns are transferred to the wafer, features also typically undergo slight comer rounding 16, that may also tend to increase the gravity of a misalignment between successive levels. When this happens, the metallization lines 12a' and 12b' will not sufficiently overlap the contact vias 14a' and 14b', thereby causing an increased resistance "R" for current passing through the contact vias. By way of example, when the metallization lines 12a' and 12b' are completely overlapping the contact vias 14a' and 14b' (i.e., in cases of no misalignments), the resistance through the contact vias is at an optimum resistance for a given semiconductor design. However, when misalignments and rounding combine to produce scenarios such as those of FIG. 1B, the resistance through the contact vias may be unacceptably high, thereby reducing performance, and in some cases causing circuit failures.
To combat this problem, FIG. 1C shows the metallization lines 12a and 12b designed with an increased width around the contact vias 14a and 14b. FIG. 1C is the computer file representation of the feature patterns before they are transferred to a wafer as described in FIG. 1B. As shown, the increased width is obtained by enlarging the size of the metallization lines by an overlap width (OLw) all the way around the contact vias 14a and 14b. Nevertheless, to maintain appropriate minimums between features (i.e., to pass a minimum spacing DRC check), the metallization lines 12a and 12b must have a minimum spacing (i.e., space (min)). Accordingly, a Pitch that is greater than Pitch.sub.2 must be satisfied between the metal lines, thereby causing a costly reduction in density throughout a device.
Because slightly higher resistance levels are becoming more acceptable in some technologies, designers have sought to increase circuit density by fabricating contacts with reduced overlap width. One way of achieving increased circuit density with reduced overlap width is to fabricate metallization lines that are just as thin as the contact vias and that extend beyond the vias as illustrated in FIG. 1D. When this is printed on the wafer, and a misalignment occurs, the resulting contact resistance is significantly less than that for the misalignment shown in FIG. 1B. This method also preserves the minimum metal pitch and thus allows a higher density layout than the technique used in FIG. 1C. Unfortunately, current DRC's do not allow the layout technique shown in FIG. 1D because the algorithms developed to check the FIG. 1C layout style are inadequate. By way of example, FIG. 1E illustrates a three step process that is currently performed by DRCs to ascertain whether to flag an error in a layout design. Initially, in an attempt to increase density, a designer may design the metallization line 12a to be just as thin as the underlying contact via 14a. Next, the DRC will take the coordinate layout of the contact via 14a and perform a "bloat operation" that produces a bloat feature 30, that is an enlarged replica of the contact via 14a. Once the bloat operation is performed, the DRC will perform a logical "AND" operation between the metallization line 12a (which contains the contact via 14a), and the bloat feature 30 to produce an "AND" result 40. In this example, the AND result 40 is defined by the logical equation Bloat {Via} AND {Metal AND Via}.
In a following operation, that is pictorially illustrated in FIG. 1F, the DRC performs a compare operation between the bloat feature 30 and the AND result 40. If the area of the bloat feature 30 is greater than the AND result 40, the DRC will flag this as a fail. On the other hand, if the metallization line 12a had been enlarged as shown in FIG. 1C, the logical "AND" operation would have produced a geometry having the same area as the bloat feature 30. As such, if these areas are equal, no fail flag would be produced. As can be appreciated, the strict operators of current DRCs pose a troubling limitation on the design of integrated circuits that demand increased circuit layout density.
In view of the foregoing, what is needed is an automated method and apparatus for checking layout mask files with DRC algorithms that enable custom checking of minimum overlapping requirements between layout mask files of different levels.